This week was pretty busy hanging out with people etc, but I got my first compiled output from my new hardware language :D
It's literally just a module with a constant output (and since it's not backed by a reg, it might not even synthesize :P), but it came from the compiler, and compiles and simulates in icarus verilog! It also required a lot of hacks and hand-holding for now in the compiler, but you gotta start somewhere. I'm also pretty certain that the 1:1 binding/verilog module correspondence is a bad idea, but I'll likely stick with it for a bit longer as it turns out to be a pretty convenient compilation unit to test with on both ends actually. I'm also holding off on doing unit tests for a bit; I'm pretty sure this syntax is what I'm after, but what exactly it represents in the AST/IL will probably be in flux for quite some time.
Anyways, not many interesting details to go into yet; the compiler's being done in haskell, using parsec as a parser. Since I haven't got much farther there isn't much yet to talk about, but I should have more info as the project moves forward. We'll see how that goes in the coming weeks, again as I really need to crack down on more demo stuff hehe.
On another more distracted note, I think I might pick up some more rubik's cube training on the side again. I finally stickered up one of my HuanYing kits, which is my favorite cube that unfortunately went out of production in favor of newer models (which reminds me, need to buy out all the old stock, even if I can't get them as DIY kits anymore!). Even just feeling the cube made me want to pick this up again, so I think I'll port my old .net trainer to angular and see how that goes. Would also probably make a nice app project in Fuse :)
Until next time!
Last Edited on Mon Jun 06 2016 04:07:08 GMT-0400 (EDT)